Flexnode’s approach delivers a strategic advantage over traditional data center construction by transferring complexity off the job site and into a controlled manufacturing environment. Our modules are engineered for speed, scalability, and geographic flexibility—purpose built to support the rapidly evolving demands of AI and high-performance compute workloads. By industrializing the data center, we ensure repeatable, high-quality outcomes that can be rapidly deployed with minimal on-site work.

AI is transforming not just what chips can do, but how we design them. This panel of top investors and semiconductor leaders will explore how AI is accelerating chip development, lowering barriers to entry, and expanding who can participate in the next era of hardware innovation.

AI is emerging as a true collaborator—capable of reasoning through design trade-offs, iterating architectures, and navigating verification alongside human engineers. This comes at a time when chip development is costly and complex, often taking 3–5 years and over $100M, with a looming shortage of 1 million skilled workers by 2030. Startups face even higher hurdles compared to industry giants with vast data and teams. Can AI level the playing field and make chip creation faster, cheaper, and more accessible?

As AI algorithms become more complex, they consume disproportionately greater run-time and energy. This makes meeting performance or efficiency goals require some level of hardware acceleration. The highest levels of performance and efficiency are achieved with custom hardware. Traditional hardware design and verification methodologies are labor-intensive and time-consuming and are not a good match for rapidly evolving AI technologies.

We will introduce the application of High-Level Synthesis (HLS) for automating many of the hardware design tasks involved in creating a bespoke accelerator. Using HLS, popular machine learning frameworks, and Quantize-Aware Training, we can build highly optimized and bit precise hardware, targeting ASIC or FPGA implementations.

Semiconductor development faces increasing complexity, faster timelines, and fierce competition, exposing the limitations of traditional EDA tools. In response, AI Agents, powered by LLMs and advanced algorithms, are emerging as next-gen solutions. This session explores how these agents surpass conventional automation by independently managing tasks like hardware modeling, constraint solving, debugging, testbench creation, and design optimization. We'll cover real-world use cases showing how AI Agents deliver improved productivity, design quality, and time-to-market, including their ability to autonomously detect bugs and optimize RTL designs.

Arm Neoverse is designed to meet these evolving needs, offering high compute density, exceptional energy efficiency, and a strong total cost of ownership (TCO). As host processors, Neoverse-based CPUs integrate seamlessly with GPUs and AI accelerators to enable flexible, power-efficient, and high-performance deployments across heterogeneous AI platforms capable of managing the complexity and coordination required by agentic AI systems.

In this session, we’ll demo an agentic AI application running on an AI server powered by Arm Neoverse as the host node. The application coordinates multiple agents to accelerate decision-making and streamline workload execution. We’ll also highlight the advantages of running agentic AI on heterogeneous infrastructure, explain why Arm CPUs are ideal as host processors, and demonstrate how Arm provides a scalable, efficient foundation for real-world enterprise and cloud environments.

AI inference costs are high and workloads are growing, especially when low latency is required. We demonstrate NorthPole's energy efficiency and high throughput for low-latency edge and datacenter inference tasks.

This hands-on session is designed for developers and architects building and scaling generative AI services. We will provide a practical look at Google Kubernetes Engine (GKE) as the foundation for high-performance large language model (LLM) inference. The session will feature a live demo of the GKE Inference Gateway, highlighting its model-aware routing and serving priority features. We will then delve into the open-source llm-d project, showcasing its vLLM-aware scheduling and disaggregated serving capabilities. To cap it off, we'll explore the impressive performance gains of running vLLM on Cloud TPUs for maximum throughput and efficiency. You will leave with actionable insights and code examples to optimize your LLM serving stack.

Innovation happens where AI meets the edge. In this interactive session, we’ll demonstrate how the Metis® platform enables breakthrough applications across industries. Discover how scalable, efficient inference unlocks new possibilities in manufacturing, logistics, energy, and beyond.

Outdated x86 CPU/NIC architectures bottleneck AI's power, limiting true Generative AI potential. NeuReality's groundbreaking NR1® Chip combines entirely new categories of AI-CPU and AI-NIC into one single chip, fundamentally redefining AI data center inference solutions. It solves these bottlenecks, boosting Generative AI token output up to 6.5x for the same cost and power versus x86 CPU systems, making AI widely affordable and accessible for businesses and governments. It works in harmony with any AI Accelerator/GPU, maximizing GPU utilization, performance, and system energy efficiency. Our NR1® Inference Appliance, with its built-in software, intuitive SDK, and APIs, comes preloaded with out-of-the-box LLMs like Llama 3, Mistral, DeepSeek, Granite, and Qwen for rapid, seamless deployment with significantly reduced complexity, cost, and power consumption at scale.